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C/C++ Source or Header  |  2000-05-04  |  22KB  |  633 lines
  1. /***************************************************************************
  2.  
  3. Seicross memory map (preliminary)
  4.  
  5. driver by Nicola Salmoria
  6.  
  7.  
  8. 0000-77ff ROM
  9. 7800-7fff RAM
  10. 9000-93ff videoram
  11. 9c00-9fff colorram
  12.  
  13. Read:
  14. A000      Joystick + Players start button
  15. A800      player #2 controls + coin + ?
  16. B000      test switches
  17. B800      watchdog reset
  18.  
  19. Write:
  20. 8820-887f Sprite ram
  21. 9800-981f Scroll control
  22. 9880-989f ? (always 0?)
  23.  
  24. I/O ports:
  25. 0         8910 control
  26. 1         8910 write
  27. 4         8910 read
  28.  
  29.  
  30. There is a microcontroller on the board. Nichibutsu custom part marked
  31. NSC81050-102  8127 E37 and labeled No. 00363.  It's a 40-pin IC at location 4F
  32. on the (Seicross-) board. Looks like it is linked to the dips (and those are
  33. on a very small daughterboard).
  34.  
  35. ***************************************************************************/
  36.  
  37. #include "driver.h"
  38. #include "vidhrdw/generic.h"
  39.  
  40.  
  41.  
  42. extern unsigned char *seicross_row_scroll;
  43. WRITE_HANDLER( seicross_colorram_w );
  44. void seicross_vh_convert_color_prom(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
  45. void seicross_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
  46.  
  47.  
  48. static unsigned char *nvram;
  49. static size_t nvram_size;
  50.  
  51.  
  52. static void nvram_handler(void *file,int read_or_write)
  53. {
  54.     if (read_or_write)
  55.         osd_fwrite(file,nvram,nvram_size);
  56.     else
  57.     {
  58.         if (file)
  59.             osd_fread(file,nvram,nvram_size);
  60.         else
  61.         {
  62.             /* fill in the default values */
  63.             memset(nvram,0,nvram_size);
  64.             nvram[0x0d] = nvram[0x0f] = nvram[0x11] = nvram[0x13] = nvram[0x15] = nvram[0x19] = 1;
  65.             nvram[0x17] = 3;
  66.         }
  67.     }
  68. }
  69.  
  70.  
  71.  
  72. static void friskyt_init_machine(void)
  73. {
  74.     /* start with the protection mcu halted */
  75.     cpu_set_halt_line(1, ASSERT_LINE);
  76. }
  77.  
  78.  
  79.  
  80. static int portb;
  81.  
  82. static READ_HANDLER( friskyt_portB_r )
  83. {
  84.     return (portb & 0x9f) | (readinputport(6) & 0x60);
  85. }
  86.  
  87. static WRITE_HANDLER( friskyt_portB_w )
  88. {
  89. //logerror("PC %04x: 8910 port B = %02x\n",cpu_get_pc(),data);
  90.     /* bit 0 is IRQ enable */
  91.     interrupt_enable_w(0,data & 1);
  92.  
  93.     /* bit 1 flips screen */
  94.  
  95.     /* bit 2 resets the microcontroller */
  96.     if (((portb & 4) == 0) && (data & 4))
  97.     {
  98.         /* reset and start the protection mcu */
  99.         cpu_set_reset_line(1, PULSE_LINE);
  100.         cpu_set_halt_line(1, CLEAR_LINE);
  101.     }
  102.  
  103.     /* other bits unknown */
  104.     portb = data;
  105. }
  106.  
  107.  
  108. static unsigned char *sharedram;
  109.  
  110. static READ_HANDLER( sharedram_r )
  111. {
  112.     return sharedram[offset];
  113. }
  114.  
  115. static WRITE_HANDLER( sharedram_w )
  116. {
  117.     sharedram[offset] = data;
  118. }
  119.  
  120.  
  121. static struct MemoryReadAddress readmem[] =
  122. {
  123.     { 0x0000, 0x77ff, MRA_ROM },
  124.     { 0x7800, 0x7fff, sharedram_r },
  125.     { 0x8820, 0x887f, MRA_RAM },
  126.     { 0x9000, 0x93ff, MRA_RAM },    /* video RAM */
  127.     { 0x9800, 0x981f, MRA_RAM },
  128.     { 0x9c00, 0x9fff, MRA_RAM },    /* color RAM */
  129.     { 0xa000, 0xa000, input_port_0_r },    /* IN0 */
  130.     { 0xa800, 0xa800, input_port_1_r },    /* IN1 */
  131.     { 0xb000, 0xb000, input_port_2_r },    /* test */
  132.     { 0xb800, 0xb800, watchdog_reset_r },
  133.     { -1 }    /* end of table */
  134. };
  135.  
  136. static struct MemoryWriteAddress writemem[] =
  137. {
  138.     { 0x0000, 0x77ff, MWA_ROM },
  139.     { 0x7800, 0x7fff, sharedram_w, &sharedram },
  140.     { 0x8820, 0x887f, MWA_RAM, &spriteram, &spriteram_size },
  141.     { 0x9000, 0x93ff, videoram_w, &videoram, &videoram_size },
  142.     { 0x9800, 0x981f, MWA_RAM, &seicross_row_scroll },
  143.     { 0x9880, 0x989f, MWA_RAM, &spriteram_2, &spriteram_2_size },
  144.     { 0x9c00, 0x9fff, seicross_colorram_w, &colorram },
  145.     { -1 }    /* end of table */
  146. };
  147.  
  148. static struct IOReadPort readport[] =
  149. {
  150.     { 0x04, 0x04, AY8910_read_port_0_r },
  151.     { 0x0c, 0x0c, AY8910_read_port_0_r },
  152.     { -1 }    /* end of table */
  153. };
  154.  
  155. static struct IOWritePort writeport[] =
  156. {
  157.     { 0x00, 0x00, AY8910_control_port_0_w },
  158.     { 0x01, 0x01, AY8910_write_port_0_w },
  159.     { 0x08, 0x08, AY8910_control_port_0_w },
  160.     { 0x09, 0x09, AY8910_write_port_0_w },
  161.     { -1 }    /* end of table */
  162. };
  163.  
  164. static struct MemoryReadAddress mcu_nvram_readmem[] =
  165. {
  166.     { 0x0000, 0x007f, MRA_RAM },
  167.     { 0x1000, 0x10ff, MRA_RAM },
  168.     { 0x8000, 0xf7ff, MRA_ROM },
  169.     { 0xf800, 0xffff, sharedram_r },
  170.     { -1 }    /* end of table */
  171. };
  172.  
  173. static struct MemoryReadAddress mcu_no_nvram_readmem[] =
  174. {
  175.     { 0x0000, 0x007f, MRA_RAM },
  176.     { 0x1003, 0x1003, input_port_3_r },    /* DSW1 */
  177.     { 0x1005, 0x1005, input_port_4_r },    /* DSW2 */
  178.     { 0x1006, 0x1006, input_port_5_r },    /* DSW3 */
  179.     { 0x8000, 0xf7ff, MRA_ROM },
  180.     { 0xf800, 0xffff, sharedram_r },
  181.     { -1 }    /* end of table */
  182. };
  183.  
  184. static struct MemoryWriteAddress mcu_nvram_writemem[] =
  185. {
  186.     { 0x0000, 0x007f, MWA_RAM },
  187.     { 0x1000, 0x10ff, MWA_RAM, &nvram, &nvram_size },
  188.     { 0x2000, 0x2000, DAC_0_data_w },
  189.     { 0x8000, 0xf7ff, MWA_ROM },
  190.     { 0xf800, 0xffff, sharedram_w },
  191.     { -1 }    /* end of table */
  192. };
  193.  
  194. static struct MemoryWriteAddress mcu_no_nvram_writemem[] =
  195. {
  196.     { 0x0000, 0x007f, MWA_RAM },
  197.     { 0x2000, 0x2000, DAC_0_data_w },
  198.     { 0x8000, 0xf7ff, MWA_ROM },
  199.     { 0xf800, 0xffff, sharedram_w },
  200.     { -1 }    /* end of table */
  201. };
  202.  
  203.  
  204.  
  205.  
  206. INPUT_PORTS_START( friskyt )
  207.     PORT_START      /* IN0 */
  208.     PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP    | IPF_8WAY )
  209.     PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN  | IPF_8WAY )
  210.     PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT  | IPF_8WAY )
  211.     PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY )
  212.     PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 )
  213.     PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN2 )
  214.     PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START1 )
  215.     PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START2 )
  216.  
  217.     PORT_START      /* IN1 */
  218.     PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_COCKTAIL )
  219.     PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_COCKTAIL )
  220.     PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_COCKTAIL )
  221.     PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
  222.     PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN3 )
  223.     PORT_SERVICE( 0x20, IP_ACTIVE_HIGH )
  224.     PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
  225.     PORT_DIPNAME( 0x80, 0x00, "Counter Check" )
  226.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  227.     PORT_DIPSETTING(    0x80, DEF_STR( On ) )
  228.  
  229.     PORT_START      /* Test */
  230.     PORT_DIPNAME( 0x01, 0x00, "Test Mode" )
  231.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  232.     PORT_DIPSETTING(    0x01, DEF_STR( On ) )
  233.     PORT_DIPNAME( 0x02, 0x00, "Connection Error" )
  234.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  235.     PORT_DIPSETTING(    0x02, DEF_STR( On ) )
  236.     PORT_BIT( 0xfc, IP_ACTIVE_HIGH, IPT_UNKNOWN )    /* probably unused */
  237. INPUT_PORTS_END
  238.  
  239. INPUT_PORTS_START( radrad )
  240.     PORT_START      /* IN0 */
  241.     PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP    | IPF_8WAY )
  242.     PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN  | IPF_8WAY )
  243.     PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT  | IPF_8WAY )
  244.     PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY )
  245.     PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
  246.     PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN1 )
  247.     PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START1 )
  248.     PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START2 )
  249.  
  250.     PORT_START      /* IN1 */
  251.     PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_COCKTAIL )
  252.     PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_COCKTAIL )
  253.     PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_COCKTAIL )
  254.     PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
  255.     PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN3 )
  256.     PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1 )
  257.     PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2 )
  258.     PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
  259.  
  260.     PORT_START      /* Test */
  261.     PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_COCKTAIL )
  262.     PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 | IPF_COCKTAIL )
  263.     PORT_BIT( 0xfc, IP_ACTIVE_HIGH, IPT_UNKNOWN )    /* probably unused */
  264.  
  265.     PORT_START    /* DSW1 */
  266.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Cabinet ) )
  267.     PORT_DIPSETTING(    0x01, DEF_STR( Upright ) )
  268.     PORT_DIPSETTING(    0x00, DEF_STR( Cocktail ) )
  269.     PORT_DIPNAME( 0x06, 0x02, DEF_STR( Lives ) )
  270.     PORT_DIPSETTING(    0x00, "2" )
  271.     PORT_DIPSETTING(    0x02, "3" )
  272.     PORT_DIPSETTING(    0x04, "4" )
  273.     PORT_DIPSETTING(    0x06, "5" )
  274.     PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
  275.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  276.     PORT_DIPSETTING(    0x08, DEF_STR( On ) )
  277.     PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
  278.  
  279.     PORT_START    /* DSW2 */
  280.     PORT_DIPNAME( 0x07, 0x00, DEF_STR( Unknown ) )
  281.     PORT_DIPSETTING(    0x00, "0" )
  282.     PORT_DIPSETTING(    0x01, "1" )
  283.     PORT_DIPSETTING(    0x02, "2" )
  284.     PORT_DIPSETTING(    0x03, "3" )
  285.     PORT_DIPSETTING(    0x04, "4" )
  286.     PORT_DIPSETTING(    0x05, "5" )
  287.     PORT_DIPSETTING(    0x06, "6" )
  288.     PORT_DIPSETTING(    0x07, "7" )
  289.     PORT_DIPNAME( 0x08, 0x08, DEF_STR( Free_Play ) )
  290.     PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
  291.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  292.     PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
  293.  
  294.     PORT_START    /* DSW3 */
  295.     PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coinage ) )
  296.     PORT_DIPSETTING(    0x08, DEF_STR( 2C_1C ) )
  297.     PORT_DIPSETTING(    0x09, DEF_STR( 2C_2C ) )
  298.     PORT_DIPSETTING(    0x00, DEF_STR( 1C_1C ) )
  299.     PORT_DIPSETTING(    0x0a, DEF_STR( 2C_3C ) )
  300.     PORT_DIPSETTING(    0x0b, DEF_STR( 2C_4C ) )
  301.     PORT_DIPSETTING(    0x01, DEF_STR( 1C_2C ) )
  302.     PORT_DIPSETTING(    0x0c, DEF_STR( 2C_5C ) )
  303.     PORT_DIPSETTING(    0x0d, DEF_STR( 2C_6C ) )
  304.     PORT_DIPSETTING(    0x02, DEF_STR( 1C_3C ) )
  305.     PORT_DIPSETTING(    0x0e, DEF_STR( 2C_7C ) )
  306.     PORT_DIPSETTING(    0x0f, DEF_STR( 2C_8C ) )
  307.     PORT_DIPSETTING(    0x03, DEF_STR( 1C_4C ) )
  308.     PORT_DIPSETTING(    0x04, DEF_STR( 1C_5C ) )
  309.     PORT_DIPSETTING(    0x05, DEF_STR( 1C_6C ) )
  310.     PORT_DIPSETTING(    0x06, DEF_STR( 1C_7C ) )
  311.     PORT_DIPSETTING(    0x07, DEF_STR( 1C_8C ) )
  312.     PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
  313. INPUT_PORTS_END
  314.  
  315. INPUT_PORTS_START( seicross )
  316.     PORT_START      /* IN0 */
  317.     PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP    | IPF_8WAY )
  318.     PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN  | IPF_8WAY )
  319.     PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT  | IPF_8WAY )
  320.     PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY )
  321.     PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 )
  322.     PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN2 )
  323.     PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START1 )
  324.     PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START2 )
  325.  
  326.     PORT_START      /* IN1 */
  327.     PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_COCKTAIL )
  328.     PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_COCKTAIL )
  329.     PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_COCKTAIL )
  330.     PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
  331.     PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN3 )
  332.     PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )    /* probably unused */
  333.     PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON1 )
  334.     PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_COCKTAIL )
  335.  
  336.     PORT_START      /* Test */
  337.     PORT_SERVICE( 0x01, IP_ACTIVE_HIGH )
  338.     PORT_DIPNAME( 0x02, 0x00, "Connection Error" )
  339.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  340.     PORT_DIPSETTING(    0x02, DEF_STR( On ) )
  341.     PORT_BIT( 0xfc, IP_ACTIVE_HIGH, IPT_UNKNOWN )    /* probably unused */
  342.  
  343.     PORT_START    /* DSW1 */
  344.     PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
  345.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  346.     PORT_DIPSETTING(    0x01, DEF_STR( On ) )
  347.     PORT_DIPNAME( 0x02, 0x00, DEF_STR( Free_Play ) )
  348.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  349.     PORT_DIPSETTING(    0x02, DEF_STR( On ) )
  350.     PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Unknown ) )
  351.     PORT_DIPSETTING(    0x00, "0" )
  352.     PORT_DIPSETTING(    0x04, "1" )
  353.     PORT_DIPSETTING(    0x08, "2" )
  354.     PORT_DIPSETTING(    0x0c, "3" )
  355.     PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
  356.  
  357.     PORT_START    /* DSW2 */
  358.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Cabinet ) )
  359.     PORT_DIPSETTING(    0x01, DEF_STR( Upright ) )
  360.     PORT_DIPSETTING(    0x00, DEF_STR( Cocktail ) )
  361.     PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
  362.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  363.     PORT_DIPSETTING(    0x02, DEF_STR( On ) )
  364.     PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Lives ) )
  365.     PORT_DIPSETTING(    0x08, "2" )
  366.     PORT_DIPSETTING(    0x00, "3" )
  367.     PORT_DIPSETTING(    0x04, "4" )
  368.     PORT_DIPSETTING(    0x0c, "5" )
  369.     PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
  370.  
  371.     PORT_START    /* DSW3 */
  372.     PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coin_B ) )
  373.     PORT_DIPSETTING(    0x03, DEF_STR( 4C_1C ) )
  374.     PORT_DIPSETTING(    0x02, DEF_STR( 3C_1C ) )
  375.     PORT_DIPSETTING(    0x01, DEF_STR( 2C_1C ) )
  376.     PORT_DIPSETTING(    0x00, DEF_STR( 1C_1C ) )
  377.     PORT_DIPNAME( 0x0c, 0x00, DEF_STR( Coin_A ) )
  378.     PORT_DIPSETTING(    0x00, DEF_STR( 1C_1C ) )
  379.     PORT_DIPSETTING(    0x04, DEF_STR( 1C_2C ) )
  380.     PORT_DIPSETTING(    0x08, DEF_STR( 1C_3C ) )
  381.     PORT_DIPSETTING(    0x0c, DEF_STR( 1C_6C ) )
  382.     PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
  383.  
  384.     PORT_START    /* Debug */
  385.     PORT_BIT( 0x1f, IP_ACTIVE_HIGH, IPT_UNKNOWN )
  386.     PORT_DIPNAME( 0x20, 0x20, "Debug Mode" )
  387.     PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
  388.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  389.     PORT_BITX(    0x40, 0x40, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Invulnerability", IP_KEY_NONE, IP_JOY_NONE )
  390.     PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
  391.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  392.     PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
  393. INPUT_PORTS_END
  394.  
  395.  
  396.  
  397. static struct GfxLayout charlayout =
  398. {
  399.     8,8,    /* 8*8 characters */
  400.     512,    /* 512 characters */
  401.     2,    /* 2 bits per pixel */
  402.     { 0, 4 },    /* the two bitplanes are packed in one byte */
  403.     { 0, 1, 2, 3, 8+0, 8+1, 8+2, 8+3 },
  404.     { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
  405.     16*8    /* every char takes 16 consecutive bytes */
  406. };
  407. static struct GfxLayout spritelayout =
  408. {
  409.     16,16,    /* 16*16 sprites */
  410.     256,    /* 256 sprites */
  411.     2,    /* 2 bits per pixel */
  412.     { 0, 4 },    /* the two bitplanes are packed in one byte */
  413.     { 0, 1, 2, 3, 8+0, 8+1, 8+2, 8+3,
  414.             16*8+0, 16*8+1, 16*8+2, 16*8+3, 17*8+0, 17*8+1, 17*8+2, 17*8+3 },
  415.     { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
  416.             16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16 },
  417.     64*8    /* every sprite takes 64 consecutive bytes */
  418. };
  419.  
  420.  
  421.  
  422. static struct GfxDecodeInfo gfxdecodeinfo[] =
  423. {
  424.     { REGION_GFX1, 0, &charlayout,   0, 16 },
  425.     { REGION_GFX1, 0, &spritelayout, 0, 16 },
  426.     { -1 } /* end of array */
  427. };
  428.  
  429.  
  430.  
  431. static struct AY8910interface ay8910_interface =
  432. {
  433.     1,    /* 1 chip */
  434.     1536000,    /* 1.536 MHz ?? */
  435.     { 25 },
  436.     { 0 },
  437.     { friskyt_portB_r },
  438.     { 0 },
  439.     { friskyt_portB_w }
  440. };
  441.  
  442. static struct DACinterface dac_interface =
  443. {
  444.     1,
  445.     { 25 }
  446. };
  447.  
  448.  
  449. #define MACHINE_DRIVER(NAME,NVRAM)                                                        \
  450. static struct MachineDriver machine_driver_##NAME =                                        \
  451. {                                                                                        \
  452.     /* basic machine hardware */                                                        \
  453.     {                                                                                    \
  454.         {                                                                                \
  455.             CPU_Z80,                                                                    \
  456.             3072000,    /* 3.072 MHz? */                                                \
  457.             readmem,writemem,readport,writeport,                                        \
  458.             interrupt,1                                                                    \
  459.         },                                                                                \
  460.         {                                                                                \
  461.             CPU_NSC8105,                                                                \
  462.             6000000/4,    /* ??? */                                                        \
  463.             mcu_##NAME##_readmem,mcu_##NAME##_writemem,0,0,                                \
  464.             ignore_interrupt,0                                                            \
  465.         }                                                                                \
  466.     },                                                                                    \
  467.     60, DEFAULT_REAL_60HZ_VBLANK_DURATION,    /* frames per second, vblank duration */    \
  468.     20,    /* 20 CPU slices per frame - an high value to ensure proper */                    \
  469.             /* synchronization of the CPUs */                                            \
  470.     friskyt_init_machine,                                                                \
  471.                                                                                         \
  472.     /* video hardware */                                                                \
  473.     32*8, 32*8, { 0*8, 32*8-1, 2*8, 30*8-1 },                                            \
  474.     gfxdecodeinfo,                                                                        \
  475.     64, 64,                                                                                \
  476.     seicross_vh_convert_color_prom,                                                        \
  477.                                                                                         \
  478.     VIDEO_TYPE_RASTER,                                                                    \
  479.     0,                                                                                    \
  480.     generic_vh_start,                                                                    \
  481.     generic_vh_stop,                                                                    \
  482.     seicross_vh_screenrefresh,                                                            \
  483.                                                                                         \
  484.     /* sound hardware */                                                                \
  485.     0,0,0,0,                                                                            \
  486.     {                                                                                    \
  487.         {                                                                                \
  488.             SOUND_AY8910,                                                                \
  489.             &ay8910_interface                                                            \
  490.         },                                                                                \
  491.         {                                                                                \
  492.             SOUND_DAC,                                                                    \
  493.             &dac_interface                                                                \
  494.         }                                                                                \
  495.     },                                                                                    \
  496.                                                                                         \
  497.     NVRAM                                                                                \
  498. };
  499.  
  500.  
  501. MACHINE_DRIVER(nvram,nvram_handler)
  502. MACHINE_DRIVER(no_nvram,0)
  503.  
  504.  
  505. /***************************************************************************
  506.  
  507.   Game driver(s)
  508.  
  509. ***************************************************************************/
  510.  
  511. ROM_START( friskyt )
  512.     ROM_REGION( 0x10000, REGION_CPU1 )    /* 64k for code */
  513.     ROM_LOAD( "ftom.01",      0x0000, 0x1000, 0xbce5d486 )
  514.     ROM_LOAD( "ftom.02",      0x1000, 0x1000, 0x63157d6e )
  515.     ROM_LOAD( "ftom.03",      0x2000, 0x1000, 0xc8d9ef2c )
  516.     ROM_LOAD( "ftom.04",      0x3000, 0x1000, 0x23a01aac )
  517.     ROM_LOAD( "ftom.05",      0x4000, 0x1000, 0xbfaf702a )
  518.     ROM_LOAD( "ftom.06",      0x5000, 0x1000, 0xbce70b9c )
  519.     ROM_LOAD( "ftom.07",      0x6000, 0x1000, 0xb2ef303a )
  520.     ROM_LOAD( "ft8_8.rom",    0x7000, 0x0800, 0x10461a24 )
  521.  
  522.     ROM_REGION( 0x10000, REGION_CPU2 )    /* 64k for the protection mcu */
  523.     /* filled in later */
  524.  
  525.     ROM_REGION( 0x4000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  526.     ROM_LOAD( "ftom.11",      0x0000, 0x1000, 0x1ec6ff65 )
  527.     ROM_LOAD( "ftom.12",      0x1000, 0x1000, 0x3b8f40b5 )
  528.     ROM_LOAD( "ftom.09",      0x2000, 0x1000, 0x60642f25 )
  529.     ROM_LOAD( "ftom.10",      0x3000, 0x1000, 0x07b9dcfc )
  530.  
  531.     ROM_REGION( 0x0040, REGION_PROMS )
  532.     ROM_LOAD( "ft.9c",        0x0000, 0x0020, 0x0032167e )
  533.     ROM_LOAD( "ft.9b",        0x0020, 0x0020, 0x6b364e69 )
  534. ROM_END
  535.  
  536. ROM_START( radrad )
  537.     ROM_REGION( 0x10000, REGION_CPU1 )    /* 64k for code */
  538.     ROM_LOAD( "1.3a",         0x0000, 0x1000, 0xb1e958ca )
  539.     ROM_LOAD( "2.3b",         0x1000, 0x1000, 0x30ba76b3 )
  540.     ROM_LOAD( "3.3c",         0x2000, 0x1000, 0x1c9f397b )
  541.     ROM_LOAD( "4.3d",         0x3000, 0x1000, 0x453966a3 )
  542.     ROM_LOAD( "5.3e",         0x4000, 0x1000, 0xc337c4bd )
  543.     ROM_LOAD( "6.3f",         0x5000, 0x1000, 0x06e15b59 )
  544.     ROM_LOAD( "7.3g",         0x6000, 0x1000, 0x02b1f9c9 )
  545.     ROM_LOAD( "8.3h",         0x7000, 0x0800, 0x911c90e8 )
  546.  
  547.     ROM_REGION( 0x10000, REGION_CPU2 )    /* 64k for the protection mcu */
  548.     /* filled in later */
  549.  
  550.     ROM_REGION( 0x4000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  551.     ROM_LOAD( "11.l7",        0x0000, 0x1000, 0x4ace7afb )
  552.     ROM_LOAD( "12.n7",        0x1000, 0x1000, 0xb19b8473 )
  553.     ROM_LOAD( "9.j7",         0x2000, 0x1000, 0x229939a3 )
  554.     ROM_LOAD( "10.j7",        0x3000, 0x1000, 0x79237913 )
  555.  
  556.     ROM_REGION( 0x0040, REGION_PROMS )
  557.     ROM_LOAD( "clr.9c",       0x0000, 0x0020, 0xc9d88422 )
  558.     ROM_LOAD( "clr.9b",       0x0020, 0x0020, 0xee81af16 )
  559. ROM_END
  560.  
  561. ROM_START( seicross )
  562.     ROM_REGION( 0x10000, REGION_CPU1 )    /* 64k for code */
  563.     ROM_LOAD( "smc1",         0x0000, 0x1000, 0xf6c3aeca )
  564.     ROM_LOAD( "smc2",         0x1000, 0x1000, 0x0ec6c218 )
  565.     ROM_LOAD( "smc3",         0x2000, 0x1000, 0xceb3c8f4 )
  566.     ROM_LOAD( "smc4",         0x3000, 0x1000, 0x3112af59 )
  567.     ROM_LOAD( "smc5",         0x4000, 0x1000, 0xb494a993 )
  568.     ROM_LOAD( "smc6",         0x5000, 0x1000, 0x09d5b9da )
  569.     ROM_LOAD( "smc7",         0x6000, 0x1000, 0x13052b03 )
  570.     ROM_LOAD( "smc8",         0x7000, 0x0800, 0x2093461d )
  571.  
  572.     ROM_REGION( 0x10000, REGION_CPU2 )    /* 64k for the protection mcu */
  573.     /* filled in later */
  574.  
  575.     ROM_REGION( 0x4000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  576.     ROM_LOAD( "sz11.7k",      0x0000, 0x1000, 0xfbd9b91d )
  577.     ROM_LOAD( "smcd",         0x1000, 0x1000, 0xc3c953c4 )
  578.     ROM_LOAD( "sz9.7j",       0x2000, 0x1000, 0x4819f0cd )
  579.     ROM_LOAD( "sz10.7h",      0x3000, 0x1000, 0x4c268778 )
  580.  
  581.     ROM_REGION( 0x0040, REGION_PROMS )
  582.     ROM_LOAD( "sz73.10c",     0x0000, 0x0020, 0x4d218a3c )
  583.     ROM_LOAD( "sz74.10b",     0x0020, 0x0020, 0xc550531c )
  584. ROM_END
  585.  
  586. ROM_START( sectrzon )
  587.     ROM_REGION( 0x10000, REGION_CPU1 )    /* 64k for code */
  588.     ROM_LOAD( "sz1.3a",       0x0000, 0x1000, 0xf0a45cb4 )
  589.     ROM_LOAD( "sz2.3c",       0x1000, 0x1000, 0xfea68ddb )
  590.     ROM_LOAD( "sz3.3d",       0x2000, 0x1000, 0xbaad4294 )
  591.     ROM_LOAD( "sz4.3e",       0x3000, 0x1000, 0x75f2ca75 )
  592.     ROM_LOAD( "sz5.3fg",      0x4000, 0x1000, 0xdc14f2c8 )
  593.     ROM_LOAD( "sz6.3h",       0x5000, 0x1000, 0x397a38c5 )
  594.     ROM_LOAD( "sz7.3i",       0x6000, 0x1000, 0x7b34dc1c )
  595.     ROM_LOAD( "sz8.3j",       0x7000, 0x0800, 0x9933526a )
  596.  
  597.     ROM_REGION( 0x10000, REGION_CPU2 )    /* 64k for the protection mcu */
  598.     /* filled in later */
  599.  
  600.     ROM_REGION( 0x4000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  601.     ROM_LOAD( "sz11.7k",      0x0000, 0x1000, 0xfbd9b91d )
  602.     ROM_LOAD( "sz12.7m",      0x1000, 0x1000, 0x2bdef9ad )
  603.     ROM_LOAD( "sz9.7j",       0x2000, 0x1000, 0x4819f0cd )
  604.     ROM_LOAD( "sz10.7h",      0x3000, 0x1000, 0x4c268778 )
  605.  
  606.     ROM_REGION( 0x0040, REGION_PROMS )
  607.     ROM_LOAD( "sz73.10c",     0x0000, 0x0020, 0x4d218a3c )
  608.     ROM_LOAD( "sz74.10b",     0x0020, 0x0020, 0xc550531c )
  609. ROM_END
  610.  
  611.  
  612.  
  613. static void init_friskyt(void)
  614. {
  615.     int A;
  616.     unsigned char *src,*dest;
  617.  
  618.     /* the protection mcu shares the main program ROMs and RAM with the main CPU. */
  619.  
  620.     /* copy over the ROMs */
  621.     src = memory_region(REGION_CPU1);
  622.     dest = memory_region(REGION_CPU2);
  623.     for (A = 0;A < 0x8000;A++)
  624.          dest[A + 0x8000] = src[A];
  625. }
  626.  
  627.  
  628.  
  629. GAMEX( 1981, friskyt,  0,        nvram,    friskyt,  friskyt, ROT0,  "Nichibutsu", "Frisky Tom", GAME_NO_COCKTAIL )
  630. GAMEX( 1982, radrad,   0,        no_nvram, radrad,   friskyt, ROT0,  "Nichibutsu USA", "Radical Radial", GAME_NO_COCKTAIL )
  631. GAMEX( 1984, seicross, 0,        no_nvram, seicross, friskyt, ROT90, "Nichibutsu + Alice", "Seicross", GAME_NO_COCKTAIL )
  632. GAMEX( 1984, sectrzon, seicross, no_nvram, seicross, friskyt, ROT90, "Nichibutsu + Alice", "Sector Zone", GAME_NO_COCKTAIL )
  633.